1. Field of the Invention
The invention pertains to the field of image sensor arrays and more particularly to CMOS image sensor array active pixel apparatus and manufacturing methods that use silicide exclusion masks for improved performance by reducing dark current leakage in critical pixel element sensor and storage areas, and for improving conductivity in unmasked areas by using silicides.
2. The Prior Art
The use of silicides in CMOS multilayer-contact technology for the reduction of the sheet resistance of thin polysilicon and shallow diffusions is well known in the art (Jaeger, R. C., "Introduction to Microelectronic Fabrication", Vol. V, Section 7.5, of Neudick, G. R. et al., editors, "Modular Series on Solid State Devices", Addison-Wesley, Reading, Mass., 1993). Interconnect delays caused by high sheet resistance and distributed capacitance of polysilicon and diffusions can limit the speed of very large scale integrated (VLSI) circuits. The effective sheet resistance is reduced by forming a low-resistivity shunting layer of silicide on their surfaces by depositing an appropriate metal using evaporation, sputtering, or chemical vapor deposition (CVD) techniques and then applying heat so that the metal reacts with the silicon (and polysilicon) and produces the desired silicide. (Silicides have also been used in bipolar processes since 1960.)
Although silicides have been used to optimize the electrical performance of standard CMOS processes, the use of silicides in CMOS active pixel sensor and storage arrays has been generally avoided because the silicide is nearly optically opaque and inhibits photon penetration into the silicon pixel sensor. Most imager publications do not mention silicides because they are not used and some explicitly mention that silicides are not used in the process. For example see Blanksby, A. J., et al., "Noise Performance of a Color CMOS Photogate Image Sensor", Proc. IEEE-IEDM 1997, p. 8.6.1, Sec. A. Monochrome Image Sensor, in which it is stated that "A 352.times.288 photogate sensor was fabricated in a Lucent Technologies non-silicided 0.8-m CMOS process . . . "
Silicides are normally applied in unmasked process steps for reducing the contact resistance and the effective sheet resistance of the source, drain, and gate. For example, the cross sectional view of FIGS. 1(a)-1(d) show the formation of silicides in an n-type MOS structure. In FIG. 1(a), transistor 100, built on a p-type substrate, has a source area 101, drain area 102, silicon dioxide (SiO.sub.2) layer 103, and polysilicon gate 110. In addition, a deposited SiO.sub.2 film 120 is included for forming an oxide spacer around gate 110. FIG. 1(b) shows the MOS structure after selective etching of SiO.sub.2 layer 120 for forming an oxide spacer 130 around polysilicon gate 110. In the next step, shown in FIG. 1(c), a suitable unmasked metallic film 150' is deposited over MOS structure 100 by evaporation, sputtering, or CVD techniques in preparation for forming a silicide film (typically CoSi.sub.2, HfSi.sub.2, MoSi.sub.2, TaSi.sub.2,TiSi.sub.2, WSi.sub.2, or ZrSi.sub.2). FIG. 1(d) shows silicide film 150 which is formed by heating (sintering). Wherever metallic film 150' is in contact with silicon substrate 101 or polysilicon 110, silicide is formed and the unreacted metallic film is removed by etching. Thus, the unmasked formation of silicides, which is commonly employed in CMOS processing, creates, without discrimination, silicides on all silicon (and polysilicon) circuit components wherever they come in contact with the silicide forming metallic layer.
In the case of circuits that include image sensor and storage circuits, silicides are not considered suitable for use in the manufacturing process because unmasked silicide formation would form photon shields over the photo-sensitive pixel cells (photodiodes). Also, silicides are commonly used beneficially under circuit contacts for reducing contact resistance and for providing a good stop for the contact etch step. However, silicide deposits also cause increased electrical leakage at any junction to which they are applied. Consequently, pixel cells are adversely effected by the increased leakage at the junctions associated with photon detection by increasing leakage (dark) current in the pixel cell.
Because the use of silicides in image pixel arrays can have beneficial effects (increased conductivity of polysilicon and diffusions) as well as detrimental effects (increased photodiode dark current and opaqueness), it is highly desirable that the beneficial effects of silicides be realized without the detrimental effects.
The present invention provides a novel strategy for selectively masking silicides in the manufacture of active pixels and active pixel arrays so that the benefits of silicides can be selectively realized while avoiding the detrimental effects.
It should be noted that this novel concept of selectively masking the formation of silicides does not conform to commonly accepted design and manufacturing rule that prohibits contact cuts for connection pads in silicide exclusion areas. Circuit and layout designers typically limit their designs to stay within the rules. Adherence to the rule ensures that the contact cut etch process, which depends on the detection of a chemical etch product that indicates when the contact cuts reach the silicide layer, has completed the contact cut. Based on the insight provided by the present invention, this design rule is violated without sacrificing reliability of the fabrication process while gaining the benefits mentioned above.